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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
2.5 V 184-pin Unbuffered DDR-I SDRAM Modules 512 MByte & 1024 MByte Modules PC1600, PC2100 & PC2700 Preliminary datasheet rev. 0.81
* 184-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity and ECC-Modules for PC and Server main memory applications * One bank 64M x 64, 64M x 72 and two bank 128M x 64, 128M x 72 organization * JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) Single + 2.5 V ( 0.2 V) power supply * Built with 512 Mbit DDR-I SDRAMs organized as 64Mb x 8 in 66-Lead TSOPII package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Performance: -6 Component Speed Grade Module Speed Grade
fCK fCK
* Auto Refresh (CBR) and Self Refresh * All inputs and outputs SSTL_2 compatible * Serial Presence Detect with E2PROM * Jedec standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. * Jedec standard reference layout * Gold plated contacts
-7 PC2100 143 133
-8 PC1600 125 100
Unit
DDR333B DDR266A DDR200 PC2700 166 133 MHz MHz
Clock Frequency (max.) @ CL = 2.5 Clock Frequency (max.) @ CL = 2
The HYS64/72D64000GU and HYS64/72D128020GU are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 64M x 64 and 128M x 64 for non-parity and 64M x 72 and 128M x 72 for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
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HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Ordering Information
Type PC2700 (CL=2.5): HYS64D128320GU-6-A HYS72D128320GU-6-A PC2100 (CL=2): HYS64D64000GU-7-A HYS72D64000GU-7-A HYS64D128020GU-7-A HYS72D128020GU-7-A PC1600 (CL=2): HYS64D64000GU-8-A HYS72D64000GU-8-A HYS64D128020GU-8-A HYS72D128020GU-8-A Note: PC1600-20220-A1 PC1600-20220-A1 PC1600-20220-B1 PC1600-20220-B1 one bank 512 MB DIMM one bank 512 MB ECC-DIMM two banks 1024 MB DIMM two banks 1024 MB ECC-DIMM 512 MBit 512 Mbit 512 MBit 512 MBit PC2100-20330-A1 PC2100-20330-A1 PC2100-20330-B1 PC2100-20330-B1 one bank 512 MB DIMM one bank 512 MB ECC-DIMM two banks 1024 MB DIMM two banks 1024 MB ECC-DIMM 512 MBit 512 Mbit 512 MBit 512 MBit PC2700-25330-B1 PC2700-25330-B1 two banks 1024 MB DIMM two banks 1024 MB ECC-DIMM 512 MBit 512 MBit Compliance Code Description SDRAM Technology
All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 72D64000GU-8-A, indicating Rev.A dies are used for the SDRAM components. The Compliance Code is printed on the module labels and describes the speed sort fe. "PC2100", the latencies (f.e. "20330" means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module.
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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0 - CKE1 DQS0 - DQS8 CLK0 - CLK2, CLK0 - CLK2 DM0 - DM8 DQS9 - DQS17 Address Inputs Bank Selects Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable SDRAM low data strobes SDRAM clock (positive lines) SDRAM clock (negative lines) SDRAM low data mask/ high data strobes S0, S1 VDD VSS VDDQ VDDID VREF VDDSPD SCL SDA SA0 - SA2 NC Chip Selects Power (+ 2.5 V) Ground I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select no connect
note: S1 and CKE1 are used on two bank modules only
Address Format
Density 512 MB 512 MB Organization 64M x 64 64M x 72 Memory Banks 1 1 2 2 SDRAMs 64M x 8 64M x 8 64M x 8 64M x 8 # of SDRAMs 8 9 16 18 # of row/bank/ columns bits 13/2/11 13/2/11 13/2/11 13/2/11 Refresh 8k 8k 8k 8k Period 64 ms 64 ms 64 ms 64 ms Interval 7.8 s 7.8 s 7.8 s 7.8 s
1024 MB 128M x 64 1024 MB 128M x 72
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HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Pin Configuration
PIN#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Frontside Symbol
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CLK1 CLK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC / CB0 NC / CB1 VDD NC / DQS8
PIN#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Frontside Symbol
A0 NC / CB2 VSS NC / CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CLK2 CLK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN#
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
Backside Symbol
VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ NC (BA2) DQ20 NC / A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 NC / CB4 NC / CB5 VDDQ CK0 CK0 VSS
PIN#
140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Backside Symbol
NC / DM8/DQS17 A10 NC / CB6 VDDQ NC / CB7 KEY VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 RAS DQ45 VDDQ S0 S1 DM5/DQS14 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC (A13) VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("no-connects") on x64 organised non-ECC modules.
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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0 DQS4 DM4/DQS13
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D0 DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D4 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D1 DQS
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D5 DQS
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D2 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D6 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D3 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D7 DQS
* Clock Wiring Serial PD SDA SCL A0 SA0 BA0 - BA1 A0 -A11, A12 VDD, VDDQ VREF VSS VDDID BA0, BA1: SDRAMs D0 - D7 A0 - A11,A12: SDRAMs D0 - D7 RAS D0 - D7 D0 - D7 D0 - D7 CAS CKE0 WE RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE : SDRAMs D0 - D7 A1 SA1 A2 SA2 Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs 2 SDRAMs 3 SDRAMs 3 SDRAMs
* Wire per Clock Loading Table/W iring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: One Bank 64M x 64 DDR-I SDRAM DIMM Module HYS64D64000GU using x8 organized SDRAMs INFINEON Technologies 5 2002-09-10 (rev.0.81)
HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D0 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D8
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D4 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D12 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D9
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D5 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D13 DQS
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D2 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D10 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D6 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D14 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D11 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D7 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15
* Clock Wiring BA0, BA1 A0 - A12 VDD, VDDQ VREF VSS VDDID BA0, BA1: SDRAMs D0, D15 A0 - A12: SDRAMs D0 - D15 SDA D0 - D15 D0 - D15 SA0 D0 - D15 SA1 SA2 SCL A0 A1 A2 Serial PD Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs 4 SDRAMs 6 SDRAMs 6 SDRAMs
* W ire per Clock Loading Table/Wiring Diagrams
CKE1 RAS CAS CKE0 WE
CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D15
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: Two Bank 128M x 64 DDR-I SDRAM DIMM Modules HYS64D128020GU using x8 Organized SDRAMs
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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0 DQS4 DM4/DQS13
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D0 DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D4 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D5 DQS
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D2 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D6 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D3 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D7 DQS
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0 - A11,A12 VDD, VDDQ VREF VSS VDDID DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 SCL A0 SA0 A1 SA1 A2 SA2 DQS Serial PD SDA
BA0, BA1: SDRAMs D0 - D8 A0 - A11, A12: SDRAMs D0 - D8 RAS D0 - D8 D0 - D8 D0 - D8 CAS CKE0 WE RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 * Clock Wiring Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs 3 SDRAMs 3 SDRAMs 3 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: One Bank 64M x 72 DDR-I SDRAM DIMM Module HYS72D64000GU using x8 organized SDRAMs INFINEON Technologies 7 2002-09-10 (rev.0.81)
HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D0 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D9
DQS4 DM4/DQS13
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D4 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D13 DQS
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D1 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D10
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D5 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D14 DQS
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D2 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D11 DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D6 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D15 DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS D12 DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D7 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D17 DQS
* Clock Wiring BA0, BA1 A0 - A12 BA0, BA1: SDRAMs D0 - D17 A0 - A12: SDRAMs D0 - D17 SDA VDD, VDDQ VREF VSS VDDID D0 - D17 D0 - D17 D0 - D17 SCL A0 SA0 A1 SA1 A2 SA2 Serial PD Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 SDRAMs 6 SDRAMs 6 SDRAMs 6 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
CKE1 RAS CAS CKE0 WE
CKE: SDRAMs D9 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D17
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: Two Bank 128M x 72 DDR-I SDRAM DIMM Modules HYS72D128020GU using x8 Organized SDRAMs
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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Clock Net Wiring
6 DRAM Loads DR AM 1 4 DRAM Loads DR AM 1
DRAM2 CK DIMM Connector CK R = 120 DRAM3 DIMM Connector DR AM4 DR AM5 R =120
DRAM2 Cap.
Cap. DR AM5
DR AM6
DRAM6 DR AM 1
3 DRAM Loads
DR AM 1
2 DRAM Loads Cap.
Cap. R =120 DIMM Connector Cap. DR AM3 DIMM Connector
R =120
Cap.
Cap. DR AM5 DR AM5 Cap. Cap.
Absolute Maximum Ratings Parameter Input / Output voltage relative to VSS Power supply voltage on VDD/VDDQ to VSS Storage temperature range Power dissipation (per SDRAM component) Data out current (short circuit) Symbol min. Limit Values max. 3.6 3.6 +150 1 50 V V
o
Unit
VIN, VOUT TSTG PD IOS
- 0.5
VDD, VDDQ - 0.5
-55 - -
C
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
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HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Supply Voltage Levels
Parameter Symbol min. Device Supply Voltage Output Supply Voltage Input Reference Voltage Termination Voltage EEPROM supply voltage
1) 2)
Limit Values nom. 2.5 2.5 0.5 x VDDQ VREF 2.5 max. 2.7 2.7 0.51 x VDDQ VREF + 0.04 3.6
Unit
Notes
VDD VDDQ VREF VTT VDDSPD
2.3 2.3 0.49 x VDDQ VREF - 0.04 2.3
V V V V V
-
1) 2) 3)
3)
Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT of the transmitting device must track VREF of the receiving device.
DC Operating Conditions (SSTL_2 Inputs) (VDDQ = 2.5 V, TA = 70 C, Voltage Referenced to VSS )
Parameter Symbol min. DC Input Logic High DC Input Logic Low Input Leakage Current Output Leakage Current
1)
Limit Values max. VDDQ + 0.3 VREF - 0.15 5 5
Unit
Notes
VIH (DC) VIL (DC) IIL IOL
VREF + 0.15 - 0.30 -5 -5
V V
1)
-
2) 2)
A A
2)
The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). For any pin under test input of 0 V VIN VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.
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HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC1600)
512MB x64 1bank -8 512MB x72 1bank -8 1GB x64 2bank -8 1GB x72 2bank -8
Symbol
Parameter/Condition
Unit
Notes
MAX
IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN Auto-Refresh Current: tRC = tRFC MIN, distributed refresh Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 1280
MAX
1440
MAX
1680
MAX
1890 mA
4
1
IDD1
1360
1530
1760
1980
mA
1, 3
IDD2P
96
108
192
216
mA
2
IDD2F
320
360
640
720
mA
2
IDD2Q
200
225
400
450
mA
2
IDD3P
128
144
256
288
mA
2
IDD3N
400
450
800
900
mA
2
IDD4R
1320
1485
1720
1935
mA
1, 3
IDD4W
1280
1440
1680
1890
mA
1
IDD5 IDD6 IDD7
2320 40 2800
2610 45 3150
2720 80 3200
3060 90 3600
mA mA mA
1
1, 3
1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10C
INFINEON Technologies
11
2002-09-10 (rev.0.81)
HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Operating, Standby and Refresh Currents (PC2100 and PC2700)
512MB 512MB 1GB x64 x64 x72 1bank 1bank 2bank -6 -7 -7 1GB 1GB 1GB x72 x64 x72 2bank 2bank 2bank -6 -7 -7 Notes
Symbol
Parameter/Condition
Unit
MAX
IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN Auto-Refresh Current: tRC = tRFC MIN, distributed refresh Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 1360
MAX
1530
MAX
2200
MAX
2475
MAX
1920
MAX
2160 mA
4
1
IDD1
1440
1620
2320
2610
2000
2250
mA
1, 3
IDD2P
112
126
288
324
224
252
mA
2
IDD2F
400
450
960
1080
800
900
mA
2
IDD2Q
224
252
640
720
448
504
mA
2
IDD3P
144
162
368
414
288
324
mA
2
IDD3N
560
630
1200
1350
1120
1260
mA
2
IDD4R
1600
1800
2560
2880
2160
2430
mA
1, 3
IDD4W
1560
1755
2480
2790
2120
2385
mA
1
IDD5 IDD6 IDD7
2480 40 3040
2790 45 3420
3280 80 3840
3690 90 4320
3040 80 3600
3420 90 4050
mA mA mA
1
1, 3
1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10C
INFINEON Technologies
12
2002-09-10 (rev.0.81)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components (for reference only)
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V)
DDR333 -6 Min tAC tDQSCK tCH tCL tHP tCK tCK tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ tQHS tQH tDQSL,H tDSS tDSH tMRD tWPRES tWPST tWPRE tIS DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period CL = 2.5 Clock cycle time CL = 2.0 DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time Address and control input hold time Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period fast slew rate slow slew rate fast slew rate slow slew rate 0.9 0.40 42 60 0.75 + 0.55 tHP-t QHS 0.35 0.2 0.2 12 0 0.40 0.25 0.75 0.60 - tHP-tQHS 0.35 0.2 0.2 14 0 0.40 0.25 0.9 1.0 0.9 1.0 0.9 0.40 45 65 1.1 0.60
120,000
Symbol
Parameter
DDR266A -7 Min
- 0.75 - 0.75
DDR200 -8 Min
- 0.8 - 0.8
Unit ns ns tCK tCK ns ns ns ns ns ns ns
Notes 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1, 10 1-4, 11 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4
Max
+ 0.7 + 0.7
Max
+ 0.75 + 0.75
Max
+ 0.8 + 0.8
- 0.7 - 0.7
0.45 0.45
0.55 0.55
0.45 0.45
0.55 0.55
0.45 0.45
0.55 0.55
min (tCL, tCH) 6 7.5 0.45 0.45 2.2 1.75
- 0.7 - 0.7 + 0.7 + 0.7
min (tCL, tCH) 7 7.5 0.5 0.5 2.2 1.75
- 0.75 - 0.75 + 0.75 + 0.75
min (t CL, tCH) 8 10 0.6 0.6 2.5 2
- 0.8 - 0.8 + 0.8 + 0.8
12 12 - -
12 12
12 12
ns ns tCK ns ns ns tCK tCK tCK ns ns
0.75
1.25
+ 0.4
0.75
1.25
+ 0.5
0.75
1.25
+ 0.6
+ 0.75 tHP-tQHS 0.35 0.2 0.2 16 0 0.60 0.40 0.25 1.1 1.1 1.1 1.1 0.9 0.40 50 70
+ 1.0
0.60
tCK tCK ns ns ns ns
2-4, 10,11
tIH tRPRE tRPST tRAS tRC
1.1 0.60
120,000
tCK tCK ns ns
1-4 1-4 1-4 1-4
INFINEON Technologies
13
2002-09-10 (rev.0.81)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Electrical Characteristics & AC Timing for DDR-I components (for reference only)
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V)
DDR333 -6 Min tRFC tRCD tRP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 512 Mbit based 72 18 18 12 15 (twr/tck) + (trp/ tck) 1 75 200 7.8 Max DDR266A -7 Min 75 20 20 15 15 (twr/tck) + (trp/ tck) 1 75 200 7.8 1 80 200 7.8 Max DDR200 -8 Min 80 20 20 15 15 Max ns ns ns ns ns tCK tCK ns tCK
s
Symbol
Parameter
Unit
Notes
1-4 1-4 1-4 1-4 1-4 1-4,9 1-4 1-4 1-4 1-4, 8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarily tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ ns, measured between VOH(ac) and VOL(ac)
INFINEON Technologies
14
2002-09-10 (rev.0.81)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC1600 Modules "-8"
Byte# Description 512MB x64 1bank -8 HEX 80 08 07 0D 0B 01 40 00 04 80 80 00 82 08 00 01 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 E8 C1 INFINEON 512MB x72 1bank -8 HEX 80 08 07 0D 0B 01 48 00 04 80 80 02 82 08 08 01 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 FA C1 INFINEON 1GB x64 2bank -8 HEX 80 08 07 0D 0B 02 40 00 04 80 80 00 82 08 00 01 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 E9 C1 INFINEON 1GB x72 2bank -8 HEX 80 08 07 0D 0B 02 48 00 04 80 80 02 82 08 08 01 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 FB C1 INFINEON
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - open for Customer use
128 256 DDR-SDRAM 13 11 1 /2 x64 / x72 0 SSTL_2.5 8 ns 0.8 ns non-ECC / ECC Self-Refresh, 7.8 ms x8 na / x8 tccd = 1 CLK 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered - 10.0 ns 0.8 ns not supported not supported 20 ns 15 ns 20 ns 50 ns 512MByte 1.1 ns 1.1 ns 0.6 ns 0.6 ns - 70 ns 80 ns 12 ns 0.6 ns 1.0 ns Revision 0.0 - - - - - - - - - -
INFINEON Technologies
15
2002-09-10 (rev.0.81)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
SPD Codes for PC2100 & PC2700 Modules "-7" & "-6"
Byte# Description 512MB x64 1bank -7 HEX 80 08 07 0D 0B 01 40 00 04 70 75 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 F3 C1 INFINEON 512MB x72 1bank -7 HEX 80 08 07 0D 0B 01 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 05 C1 INFINEON 1GB x64 2bank -7 HEX 80 08 07 0D 0B 02 40 00 04 70 75 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 F4 C1 INFINEON 1GB x72 2bank -7 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 08 08 01 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 06 C1 INFINEON 1GB x64 2bank -6 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 42 C1 INFINEON 1GB x72 2bank -6 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 54 C1 INFINEON
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255
Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number - open for Customer use
128 256 DDR-SDRAM 13 11 1 /2 x64 / x72 0 SSTL_2.5 7 ns 0.75 ns non-ECC / ECC Self-Refresh, 7.8 ms x8 na / x8 tccd = 1 CLK 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered - 7.5 ns 0.75 ns not supported not supported 20 ns 15 ns 20 ns 45 ns 512MByte 0.9 ns 0.9 ns 0.5 ns 0.5 ns - 65 ns 75 ns 12 ns 0.5 ns 0.75 ns - Revision 0.0 - - - - - - - - - -
INFINEON Technologies
16
2002-09-10 (rev.0.81)
HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Package Outlines -Raw Card A1 (One Bank Modules) DDR-SDRAM DIMM Module Package
133.35 + 0.15
4.0 max.
Front View
+ 0.13 -
4.0
*) 2.3 typ.
31.75
pin 1 64.77
2.3 typ.
52
53 49.53
92
1.27 + 0.1
6.62
Backside View
pin 93 17.80 10.0 144 145 184
2.5D
3 *) on ECC modules only
3
Detail of Contacts A 0.20 + 0.15 2.5 + 0.20 -
Detail of Contacts B 6.35 0.9R 3.8 typ. 1.8 2.175
L-DIM-18429
1+ 0.05
1.27
INFINEON Technologies
17
2002-09-10 (rev.0.81)
HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules
Package Outlines - Raw Card B1 (Two Bank Modules) DDR-SDRAM DIMM Module Package
two bank modules
133.35 + 0.15
4.0 max.
Front View
+ 0.13 -
4.0
*) 2.3 typ.
31.75
pin 1 64.77
2.3 typ.
52
53 49.53
92
1.27 + 0.1
6.62
Backside View
pin 93 17.80 10.0 144 145 184
2.5D
*)
3 *) on ECC modules only
3
Detail of Contacts A 0.20 + 0.15 2.5 + 0.20 -
Detail of Contacts B 6.35 0.9R 3.8 typ. 1.8 2.175
L-DIM-1849d
1 + 0.05
1.27
INFINEON Technologies
18
2002-09-10 (rev.0.81)

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